1. Field of the Invention
The present invention relates to reset circuits and particularly to reset circuits used when ramping up the power supply voltage of a integrated circuit device.
2. State of the Art
In digital integrated circuits (ICs) it is often desirable, upon powering up, to reset portions of the IC so that given logic within the circuit is in a known state. However, when powering up an integrated circuit, the power supply voltage is often ramped up to the intended full level of the power supply voltage instead of directly applying full power. During this time, the integrated circuit is in an intermediate state and any reset signal generated while the circuit is being powered up may appear to be at a digital level other than the intended reset digital level. Consequently, the reset signal is generally provided to the remainder of the integrated circuit a short delay time after the power supply voltage has been applied to the power supply ports.
In general, reset circuitry (referred to as power-on reset (POR) circuitry) detects the power supply voltage as its being ramped to full power and delays the application of the reset signal for a given amount of time after the power supply has been applied. Currently, PORs are implemented as a RC circuit made up of resistive and capacitive elements. The power supply voltage is coupled to the input of the POR and the output of the POR is a delayed power supply signal which functions to reset the IC.
The physical appearance of the IC layout of the standard analog POR is easily identifiable within the integrated circuit chip. Specifically, when viewing an integrated digital circuit with a microscope, it is possible to identify the capacitive and resistive layout elements that make up the POR. In addition, the POR clearly appears as an analog circuit when compared to the remaining digital circuitry making up the IC. The disadvantage of being able to visually identify where the POR is located on the IC is that it provides a manner in which to determine other architectural aspects of the IC and potentially provides a manner in which to access the IC in a way not intended by the manufacturer. It is well known in the integrated circuit industry that reverse engineering has become a prevalent concern for IC designers and manufacturers and identifying the POR location is one means in which reverse engineering can be facilitated. Furthermore, knowing the location of the POR on a digital circuit can also provide a way in which to access or alter information stored within the integrated circuit thus presenting a potential security problem.
The present invention is a method of designing a POR to make it difficult or impossible to visually detect and locate within an integrated circuit layout.